Electrostatic discharge protection device
US5714784A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 19, 1995 |
| Grant date | Feb 3, 1998 |
| Priority date | — |
| Expiry date | Oct 19, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
Abstract
The present invention is an electronic device, and more particularly an MOS transistor. A square-type layout style is used to realize the MOS device. By using the present layout style, the output driving/sinking capability of output buffers as well as the ESD protection capability of NMOS and PMOS devices in output buffers or input ESD protection circuits are significantly improved within smaller layout area. Both drain diffusion area and drain-to-bulk parasitic capacitance at the output node are reduced by this square-type layout. Devices using the present layout style can be assembled to form larger, rectangular (or square) and similarly functioning devices. Thus, the present square-type layout style is very attractive to submicron CMOS VLSI/ULSI in high-density and high-speed applications.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.