Semiconductor device with a reduced element isolation region
US5714787A · kind A · utility
3Cited by
1References
26Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 5, 1995 |
| Grant date | Feb 3, 1998 |
| Priority date | — |
| Expiry date | Dec 5, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/765
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In a semiconductor device and a method for manufacturing the semiconductor device, a width of an element isolation region is reduced by a field-shield. A silicon oxide film of a side wall of a polycrystal silicon film is fabricated by thermally oxidizing a side wall of the polycrystal silicon film, while using a silicon nitride film as an antioxidation film. A width of a field-shield electrode made of the polycrystal silicon film is made smaller than a limit value of the very fine processing.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.