Semiconductor memory device
US5715190A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 4, 1996 |
| Grant date | Feb 3, 1998 |
| Priority date | — |
| Expiry date | Jun 4, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/22
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory matrix--which comprises memory cells arranged in matrix, each made up of a ferroelectric capacitor and an address selection MOSFET--is divided for each word line into a plurality of memory blocks. Each of the memory blocks is provided with a mode storage circuit that stores a DRAM mode (volatile mode) or an NV mode (non-volatile mode) in one-to-one correspondence for each memory block, and with a refresh operation count circuit that counts for each memory block the number of times the refresh operations is performed consecutively. During an n-th refresh operation (where n is a predetermined number of times), a memory access is made to temporarily change the plate voltage of the ferroelectric capacitor from one voltage to another and at the same time the mode storage circuit is changed from the DRAM mode to the NV mode. When a read or write operation to and from a memory cell in the memory block is performed, the mode storage circuit is changed from the NV mode to the DRAM mode. The refresh operation is omitted for the memory block that was set to the NV mode according to the stored information in the mode storage circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.