Flash memory system and method for monitoring the disturb effect on memory cell blocks due to high voltage conditions of other memory cell blocks
US5715193A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | May 23, 1996 |
| Grant date | Feb 3, 1998 |
| Priority date | — |
| Expiry date | May 23, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/88
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory circuit including at least one of flash memory calls organized into one or more physically separate decode blocks and a controller which monitors the disturb effect on each independently erasable "erase" block of cells of each decode block due to erasures of other erase blocks in the same decode block, and a method of operating such a circuit. Preferably, the controller controls memory operations of each array in addition to monitoring the disturb effect on each erase block. The disturb effect causes cells of an erase block to lose charge from their floating gates each time an erase operation is performed on another erase block in the same decode block. Preferably, each time an erase block is erased, the controller updates a table for the decode block which contains the erased block by adding a unit of disturb to the count for each other erase block in the decode block and resetting the count for the erased block to zero. Also preferably, the controller performs a refresh operation on each erase block whose disturb count reaches a predetermined maximum value. During the refresh operation, any necessary recovery procedures are performed to restore the proper charge to the f…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.