Memory devices
US5715200A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 1, 1996 |
| Grant date | Feb 3, 1998 |
| Priority date | — |
| Expiry date | Oct 1, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0893
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device with a dynamic random access memory (DRAM) having an array of a plurality of rows and columns of memory elements; a cache memory formed integrally with the DRAM and includinmg at least one register with a plurality of memory elements and connected in pitch-matched relation to the DRAM array, the number of memory elements in a row of the DRAM being n times the number of memory elements in the at least one register, n being an integer greater than or equal to 2; and a connector for connecting the at least one register to the DRAM, the connector for the at least one register being a bus having a width corresponding to the number of memory elements therein.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.