Apparatus and method for prefetching data into an external cache
US5715425A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 22, 1996 |
| Grant date | Feb 3, 1998 |
| Priority date | — |
| Expiry date | Feb 22, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/6028
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A central processing unit is connected to an external memory including system memory and an external cache. The central processing unit includes a First-In-First-Out (FIFO) load buffer configured to generate an access to the external memory in response to a data prefetch command. The access to external memory has an associated data load latency period as data is moved from the system memory into the external cache. Instead of requiring the access to external memory to be completed before another FIFO load buffer address is processed, as is typically required in a FIFO load buffer configuration, the FIFO load buffer responds to the data prefetch command by processing additional stored addresses during the data load latency period.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.