Array with amorphous silicon TFTs in which channel leads overlap insulating region no more than maximum overlap
US5717223A · kind A · utility
22Cited by
10References
16Claims
0Family size
Assignee
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Key dates
| Filing date | Dec 22, 1995 |
| Grant date | Feb 10, 1998 |
| Priority date | — |
| Expiry date | Dec 22, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/6746
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
An array includes cells, each with a bottom gate amorphous silicon thin film transistor (a-Si TFT). Each a-Si TFT has an undoped amorphous silicon layer over its gate region and extending beyond its edges. Each a-Si TFT also has an insulating region with edges approximately aligned with the edges of its gate region. Two channel leads of doped semiconductor material such as microcrystalline silicon or polycrystalline silicon are on the undoped amorphous silicon layer, each overlapping an edge of the insulating region by a distance that is no more than a maximum overlap distance, which in turn is no more than 1.0 .mu.m.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.