Solid state imager device having A/D converter
US5717459A · kind A · utility
Assignees
Inventors
Key dates
| Filing date | Apr 29, 1996 |
| Grant date | Feb 10, 1998 |
| Priority date | — |
| Expiry date | Apr 29, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N25/75
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A solid state imager device such as a CCD imager device includes a timing generator which generates and supplies a clamping circuit with, a clamping pulse for clamping a first signal, corresponding to one pixel, from a through region of a CCD shift register, and a clamping pulse for clamping a second signal, corresponding to one pixel, from an optical black region of a sensor array. Specifically, the clamping pulse for clamping the first signal clamps a signal, corresponding to a first pixel, from the through region, and the clamping pulse for clamping the second signal clamps a signal, corresponding to a second or following pixel, from the optical black region. An output signal from the clamping circuit is supplied to an A/D converter which converts the supplied signal at such timing as not to sample the signal, corresponding to the first pixel, from the through region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.