EEPROM memory with contactless memory cells
US5717636A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 3, 1996 |
| Grant date | Feb 10, 1998 |
| Priority date | — |
| Expiry date | May 3, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B69/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a flash-EEPROM array, the cells in each row are grouped into pairs connected to the same diffused source line and to two different diffused bit lines, and the adjacent pairs of cells are spaced so that, in each row, only one cell is connected to a respective diffused bit line. The array presents global bit lines in the form of metal lines, and each connected to a plurality of diffused local bit lines, at least one for each sector. For each sector and each global bit line, there are provided two diffused local bit lines connected to the same respective global bit line by selection transistors so that only one local bit line is biased each time.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.