Apparatus and method for testing interconnections between semiconductor devices
US5717701A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 13, 1996 |
| Grant date | Feb 10, 1998 |
| Priority date | — |
| Expiry date | Aug 13, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/31855
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A boundary scan register allows for simplified testing of interconnections between integrated circuits. The interconnections between integrated circuits are characterized according to net type. Each net type has one or more mask registers that drive control inputs to each boundary scan register that drives a net of that type. One integrated circuit is configured to drive, while the others are configured to receive. The boundary scan registers are initialized to predetermined values, the mask registers are loaded, and clocks are pulsed to perform the needed tests. The results are then scanned out of the boundary scan registers, and a compression circuit compresses the test results data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.