Computing device having semi-dedicated high speed bus
US5717875A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 22, 1995 |
| Grant date | Feb 10, 1998 |
| Priority date | — |
| Expiry date | Sep 22, 2015 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An improved bus architecture is provided in which the bus connects a single master to multiple targets including one primary target. Bus usage is predominately between the master and one primary target at a very high data transfer rate. Traffic between the master and other secondary targets has a much lower bandwidth requirement. The bus uses a single frequency clock for transfers involving the primary target and transfers involving the secondary targets. In accordance with one embodiment of the invention, the master is connected to the primary high bandwidth target using a high speed protocol and separate read and write data paths which are always driven (i.e., never tri-stated). Always driving the high speed data paths avoids the increased area and decreased performance that would be entailed by adding additional gating. The lower bandwidth targets are supported on a single bi-directional data path to minimize area. This lower bandwidth path has a different protocol and is only activated upon command from the master in order to reduce power dissipation. This construction is different from a bus bridge in that the master specifically initiates activity on the low bandwidth bus, ba…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.