Method for etching polymer-assisted reduced small contacts for ultra large scale integration semiconductor devices
US5719089A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 21, 1996 |
| Grant date | Feb 17, 1998 |
| Priority date | — |
| Expiry date | Jun 21, 2016 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/947
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for fabricating small contact openings in the polysilicon/metal 1 dielectric (PMD) layer on semiconductor substrates using polymer sidewall spacers was achieved. This extends the current photoresist resolution limits while simplifying the manufacturing process. The method involves depositing a polysilicon layer on the PMD layer and using a photoresist mask having openings over device contact areas in the substrate. The polysilicon layer is then patterned to form openings with vertical sidewalls to the PMD insulating layer. The contact openings are then anisotropically plasma etched in a gas mixture that simultaneously forms polymer sidewall spacers on the sidewalls in the openings in the polysilicon layer. These sidewall spacers further reduce the contact opening size. The remaining photoresist layer and polymer sidewall spacers are simultaneously removed to complete the narrow contact openings. This method eliminates the need to use an additional deposition and etch-back step to form the sidewalls. A metal layer is then deposited and patterned to form the metal contacts and first level of interconnections.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.