DMOS transistor with low on-resistance and method of fabrication

US5719421A · kind A · utility

Assignee

• TEXAS INSTRUMENTS INCORPORATED · US

Inventors

• Louis N. Hutter · Richardson, US
• John P. Erdeljac · Plano, US

Key dates

• Filing date: Dec 31, 1996
• Grant date: Feb 17, 1998
• Expiry date: Dec 31, 2016

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/516

Abstract

A DMOS transistor (50) includes an Nwell (70); a Dwell (76) formed in the Nwell (70); a source region (78) formed in the Dwell (78), a channel region (80) defined between an edge of the source region (78) and an edge of the Nwell (70); a gate (86) extending over the channel region (80); and a p+ backgate contact region (90) formed in the source region (78) so as to counterdope and extend through a first portion of the source region (78) to contact the Dwell (76). The formation of the p+ backgate contact region through the source region (78) eliminates the need for a large annular shaped source region resulting in a considerable reduction in both device area and on-resistance.