Multilayer interconnect structure for semiconductor device and method of manufacturing same
US5719446A · kind A · utility
31Cited by
18References
7Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 12, 1997 |
| Grant date | Feb 17, 1998 |
| Priority date | — |
| Expiry date | Feb 12, 2017 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S257/915
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A multilayer interconnect structure for a semiconductor device. The structure comprises a lower patterned metallization layer, a higher patterned metallization layer, and filled holes for electrically interconnecting these two layers. The two metallization layers are formed out of aluminum or an aluminum alloy by high-temperature aluminum sputtering or aluminum reflow techniques. A suction-preventing layer is formed either at the bottoms of the contact holes or on the surface of the lower metallization layer to prevent the material of the lower metallization layer from being sucked into the overlying contact holes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.