Semiconductor device with increased parasitic emitter resistance and improved latch-up immunity
US5721445A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 2, 1995 |
| Grant date | Feb 24, 1998 |
| Priority date | — |
| Expiry date | Mar 2, 2015 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S257/903
Abstract
An apparatus and method for providing improved latch-up immunity in a semiconductor device such as a complementary metal-oxide-semiconductor (CMOS) integrated circuit. An exemplary apparatus includes a first region of semiconductor material of a first conductivity type, a well of semiconductor material formed in the first region and having a second conductivity type opposite to the first conductivity type, a first MOS transistor formed in the well and including a source region and a drain region formed of semiconductor material of the first conductivity type, and a second MOS transistor formed in the first region and having a source region and a drain region formed of semiconductor material of the second conductivity type. A conductive material or other suitable routing means is connected between the source region of one of the first or second MOS transistors and a corresponding voltage supply input of the device. In one embodiment, the routing means is formed of a semiconductor material having the same conductivity type as the source region, and may be a P.sup.+ or N.sup.+ active region. The source region of the first and/or second MOS transistor may be formed from a portion of th…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.