Erase voltage control circuit for an electrically erasable non-volatile memory cell
US5721707A · kind A · utility
10Cited by
2References
23Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 23, 1997 |
| Grant date | Feb 24, 1998 |
| Priority date | — |
| Expiry date | Jan 23, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/14
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An erase voltage control circuit for an electrically erasable non-volatile memory cell having a control electrode and a first electrode. The circuit includes negative voltage generator means for generating a negative erase voltage to be supplied to the control electrode of the memory cell and means for electrically coupling the first electrode to a voltage supply. The circuit further includes control means for selectively deactivating the negative voltage generator means when a current supplied by the voltage supply to the first electrode of the memory cell reaches a predetermined value.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.