Prefetching instructions between caches
US5721864A · kind A · utility
27Cited by
10References
15Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 18, 1995 |
| Grant date | Feb 24, 1998 |
| Priority date | — |
| Expiry date | Sep 18, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0862
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for selectively pre-fetching Line M+1 into an L1 instruction cache from an L2 cache or from main memory during the execution of Line M. If unresolved branches exist in pending Line M, Line M+1 is speculative and may be pre-fetched into L1 instruction cache only from L2 cache, not from main memory. Unresolved branches in pending Line M are resolved before Line M+1 is pre-fetched from main memory. If no unresolved branches exist, Line M is committed ("inevitable-speculative") and is pre-fetched from main memory. In this way, no potentially wasteful pre-fetches are performed and main memory bandwidth is preserved.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.