Method to incorporate non-volatile memory and logic components into a single sub-0.3 micron fabrication process for embedded non-volatile memory

US5723355A · kind A · utility

Assignee

• Programmable Microelectronics Corporation · US

Inventors

• Shang-De Ted Chang · Fremont, US
• Binh Ly · San Jose, US

Key dates

• Filing date: Jan 17, 1997
• Grant date: Mar 3, 1998
• Expiry date: Jan 17, 2017

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B41/49

Abstract

A semiconductor fabrication process allows for the fabrication of high-voltage transistors, logic transistors, and memory cells where, as required for sub-0.3 micron device geometries, the gate oxide of the logic transistors is thinner than the tunnel oxide thickness of the non-volatile memory cells without the undesirable contamination of the gate oxide of the logic transistors or contamination of the tunnel oxide of the memory cells. In one embodiment, the tunnel oxide of the memory cells is grown to a desired thickness. In a next step, a layer of doped polysilicon which will serve as the floating gate of the memory cell(s) is immediately deposited over the tunnel oxide of the memory cells, thereby protecting the tunnel oxide from contamination in subsequent masking and etching steps. The gate oxide of the logic transistors and the gate oxide of the high-voltage transistors are then grown to a desired thickness.