Thin film transistor with vertical channel adjacent sidewall of gate electrode and method of making
US5723879A · kind A · utility
4Cited by
1References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 24, 1997 |
| Grant date | Mar 3, 1998 |
| Priority date | — |
| Expiry date | Jan 24, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/6728
Abstract
A thin film transistor and a method which forms a channel region (c), a lightly doped drain region (LDD) region and, optionally, an offset region (o), in a portion of a semiconductor layer which is adjacent a sidewall of the gate electrode without the use of photo masks, thereby increasing the permissible degree of miniaturization and improving production yield.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.