CMOS with parasitic bipolar transistor
US5723988A · kind A · utility
1Cited by
6References
6Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 20, 1993 |
| Grant date | Mar 3, 1998 |
| Priority date | — |
| Expiry date | Oct 20, 2013 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K17/567
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A device is disclosed which combines the advantages of CMOS and bipolar using an existing parasitic bipolar device. As such high on-chip density is attainable with the device along with high speed capability while maintaining low power advantages.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.