Level boost restoration circuit
US5723994A · kind A · utility
8Cited by
8References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 10, 1996 |
| Grant date | Mar 3, 1998 |
| Priority date | — |
| Expiry date | Jun 10, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/01721
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A spurious glitch elongation circuit is described. The spurious glitch elongation circuit will allow the restoration of the output level of a level boost driving circuit. The circuit has a one-sided delay chain to increase the pulse width of spurious glitches that are from one logic state to a second logic state and return to the first logic state, while minimizing spurious glitches that are from the second logic state to the first logic state and returned to the second logic state.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.