Logic block structure optimized for sum generation
US5724276A · kind A · utility
93Cited by
4References
3Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 17, 1996 |
| Grant date | Mar 3, 1998 |
| Priority date | — |
| Expiry date | Jun 17, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2207/4812
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention is part of a Field Programmable Gate Array logic block which performs arithmetic functions as well as logic functions. The novel structure includes a small amount of extra hardware which can implement the XOR function as well as several other useful functions. With the invention, one-bit adders can be generated using only a single lookup table, a carry multiplexer, and the extra hardware. N-bit adders can be implemented with N lookup tables. Multipliers, adders, counters, loadable synchronous set-reset counters and many other common functions are all more efficiently implemented with the invention.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.