Method of fabricating a dynamic random access memory (DRAM) cell capacitor using hemispherical grain (HSG) polysilicon and selective polysilicon etchback

US5726085A · kind A · utility

Inventors

• Darius Crenshaw · Allen, US
• Rick L. Wise · Fairview, US
• Jeffrey McKee · Meridian, US

Key dates

• Filing date: Mar 9, 1995
• Grant date: Mar 10, 1998
• Expiry date: Mar 9, 2015

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D1/716

Abstract

A storage node 64 of a capacitor having increased charge storage capacity and a method for forming thereof. A doped polysilicon region 68 is formed. A thin layer of hemispherical grain polysilicon 70 is deposited over the doped polysilicon region 68. The doped polysilicon region 68 and the thin layer of hemispherical grain polysilicon 70 are etched using an etch chemistry that etches the doped polysilicon region 68 faster than the thin layer of hemispherical grain polysilicon 70 to increase the surface area of an upper surface 66 of the storage node 64.