Self-timed circuit control device and method
US5729160A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jul 20, 1994 |
| Grant date | Mar 17, 1998 |
| Priority date | — |
| Expiry date | Jul 20, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1051
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A device and method for self-timed, temporary disabling or latching of an electric circuit. A first portion of the circuit has sensing means for sensing a change in the value of an output signal of a second circuit portion corresponding to a change between logic states. The first circuit portion also includes immobilizing means responsive to the sensing means for temporarily disabling or latching the second circuit portion. The immobilizing means functions after such a change in logic state has occurred and, in addition, when the output signal of the second circuit portion has acquired a value corresponding to a predetermined logic state. Disabling occurs when the immobilizing means turns off a switch of the second portion. Latching occurs when the immobilizing means activates latch means of the second portion, thereby fixing voltage level(s) and corresponding logic state(s).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.