Data processing with first level cache bypassing after a data transfer becomes excessively long
US5729713A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Mar 27, 1995 |
| Grant date | Mar 17, 1998 |
| Priority date | — |
| Expiry date | Mar 27, 2015 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The hit rate of a cache memory (43) is improved by monitoring data transfer commands on a command bus (51) by Non-Cache circuitry (45A). Cache data replacements are inhibited after a consecutive sequence of data transfers which exceeds a threshold number of data transfers are detected by Non-Cache circuitry (45A). The threshold number is selected to be an amount of data transfers which is large enough to imply that a large block of data is being transferred. Such large data blocks tend to flush the cache and reduce subsequent cache hit rate. Other sources of cache inhibit signals may be included, such as System Cache Enable (SKEN), to inhibit caching for other reasons, such as when non-cacheable areas such as video memory are being accessed. Inhibiting useless cache data replacements in this manner improves hit rate and reduces power consumption.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.