Integrated pad and fuse structure for planar copper metallurgy
US5731624A · kind A · utility
22Cited by
5References
10Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 28, 1996 |
| Grant date | Mar 24, 1998 |
| Priority date | — |
| Expiry date | Jun 28, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor interconnection consists of a corrosion resistant integrated fuse and Controlled, Collapse Chip Connection (C4) structure for the planar copper Back End of Line (BEOL). Non copper fuse material is directly connected to copper wiring.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.