Electrolytic method of depositing gold connectors on a printed circuit board
US5733466A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 6, 1996 |
| Grant date | Mar 31, 1998 |
| Priority date | — |
| Expiry date | Feb 6, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2203/1476
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
Electrodepositing a metallurgy such as gold on to printed circuit board features. The methods include electrolessly depositing a copper layer over the surface of the printed circuit board. This is followed by applying a layer of photoresist atop the electroless copper, and exposing and developing the photoresist to uncover areas to be etched, leaving behind the specific features to be plated. By this expedient the remaining copper forms a commoning layer. The remaining photoresist is stripped to uncover the copper commoning layer, and a second layer of photoresist is applied atop the partially etched copper layer. This layer of photoresist is exposed and developed to uncover the features to be plated. These features are then plated with the metallurgy of choice. The photoresist is then stripped off and the electroless copper layer can remain if needed for further processing or be microetched off without harming copper traces that may exist below the electroless copper layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.