Method of fabricating a MOS read-only semiconductor memory array
US5733795A · kind A · utility
4Cited by
3References
9Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 22, 1996 |
| Grant date | Mar 31, 1998 |
| Priority date | — |
| Expiry date | Apr 22, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B20/00
Abstract
A method is described for a read-only MOS semiconductor memory. An addressable array of a multiplicity of cells each comprising a single MOS transistor is coded for preselected cells by providing them with source/drain regions which are spaced apart from edges of their respective overlying gate electrode regions. This is accomplished by a masking step late in the fabrication sequence. In this way, a dense MOS memory having rapid manufacturing turn-around is provided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.