CMOS voltage clamp

US5734186A · kind A · utility

Assignee

• DELCO ELECTRONICS CORPORATION · US

Inventors

• Edward H. Honnigford · Russiaville, US
• Tracy Adam Noll · Kokomo, US
• Jack D. Parrish · Kokomo, US

Key dates

• Filing date: Sep 16, 1996
• Grant date: Mar 31, 1998
• Expiry date: Sep 16, 2016

Classification

• Technology area (CPC Y): Emerging Cross-Sectional Technologies
• CPC primary: Y10S148/009

Abstract

An IC voltage clamp and a process for forming the voltage clamp. The voltage clamp includes an MGFO device having an n-type source region, an n-type drain region, and a p-type field implant diffusion between the source and drain regions. The voltage clamp further employs a parasitic NPN device having a collector region coincident with the MGFO drain region, an emitter region coincident with the MGFO source region, and a base region formed by the substrate. A metal gate electrode overlies and is insulated from the field implant diffusion, but electrically connects the source and emitter regions to ground. An input electrode contacts the drain region so as to electrically connect the drain and collector regions to the input voltage of an integrated circuit. The field implant diffusion and drain/collector regions are formed by overlapping their masks, such that a lower breakdown voltage is achieved between the NPN collector and the substrate and field implant diffusion (the NPN base). The voltage clamp is capable of withstanding electrostatic discharge pulses of greater than about 8000 Vdc, and is particularly adapted for use in protecting a CMOS IC that operates at high voltages, suc…