Memory cell design with vertically stacked crossovers

US5734187A · kind A · utility

Assignee

• Intel Corporation · US

Inventors

• Mark Bohr · Beaverton, US
• Jeffrey K. Greason · Portland, US

Key dates

• Filing date: Jun 16, 1997
• Grant date: Mar 31, 1998
• Expiry date: Jun 16, 2017

Classification

• Technology area (CPC Y): Emerging Cross-Sectional Technologies
• CPC primary: Y10S257/904

Abstract

A memory cell with vertically stacked crossovers. In prior memory cells, crossover connections within the memory cell were implemented in the same device layer. This wasted valuable design space, since the crossovers were therefore required to sit side-by-side in the layout design. The present invention implements crossovers in different materials on different device layers. The crossovers may therefore be vertically stacked on top of each other, reducing the area of the memory cell.