Patent · US Expired

Method and system for layout and schematic generation for heterogeneous arrays

US5734582A · kind A · utility

9Cited by
14References
32Claims
0Family size

Assignee

Inventors

Key dates

Filing dateDec 12, 1995
Grant dateMar 31, 1998
Priority date
Expiry dateDec 12, 2015

Classification

  • Technology area (CPC G)Physics
  • CPC primaryG06F30/39
  • WIPO fieldComputer technology
  • WIPO sectorElectrical engineering

Abstract

A method and system for defining, placing and routing kernels for a family of integrated circuits is provided. The integrated circuits are defined using repeatable row and column circuit types. Kernels are defined by the intersections of the row and column circuit types in the array. The kernels are placed and routed automatically for each member of the family of integrated circuit arrays, each member being generally characterized by a different size, i.e., a different number of repeatable row or column circuit types.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.