Method and apparatus for providing external access to internal integrated circuit test circuits
US5734661A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 20, 1996 |
| Grant date | Mar 31, 1998 |
| Priority date | — |
| Expiry date | Sep 20, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/2273
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated circuit includes an integrated circuit die mounted in a package having a plurality of externally accessible contacts. A functional circuit, such as a memory circuit, is formed on the integrated circuit die and is coupled through bonding pads to the external contacts of the integrated circuit. A test circuit is also formed on the integrated circuit die to allow performance parameters to be determined by performing tests on the test circuit when the test circuit is in wafer form before packaging. To allow tests to be performed on the test circuit after packaging, a switch circuit formed on the integrated circuit die selectively couples input/output terminals of the test circuit to respective bonding pads that are connected to the externally accessible contacts. The switch circuit is operated by a switch controller, which may be a decoder that responds to a pattern of signals or a sequence of signals applied to the externally accessible contacts or an overvoltage detector that responds to a voltage outside a range of operating voltages for the functional circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.