Process for fabricating a fully self-aligned soi mosfet
US5736435A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 3, 1995 |
| Grant date | Apr 7, 1998 |
| Priority date | — |
| Expiry date | Jul 3, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/01
Abstract
A process for fabricating a MOSFET on an SOI substrate includes the formation of an active region (14) isolated by field isolation regions (16, 18) and by an insulating layer (12). A recess (26) is formed in the active region (14) using a masking layer (22) having an opening (24) therein. A gate dielectric layer (32) is formed in the recess (26) and a polycrystalline silicon layer (34) is deposited to overlie the masking layer (22), and to fill the recess (26). A planarization process is carried out to form a gate electrode (36) in the recess (26), and source and drain regions (40, 42) are formed in a self-aligned manner to the gate electrode (36). A channel region (44) resides intermediate to the source and drain regions (40, 42) and directly below the gate electrode (36).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.