Semiconductor memory device having improved isolation between electrodes, and process for fabricating the same
US5736449A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 26, 1996 |
| Grant date | Apr 7, 1998 |
| Priority date | — |
| Expiry date | Jan 26, 2016 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/974
Abstract
With recent decreases in the size of semiconductor memories, isolation problems typically arise during fabrication of a capacitor for a high-capacity semiconductor memory device. To overcome this, arrangements are provided to improve the isolation between capacitor elements even if those elements are extremely close together. For example, if a material such as platinum is used as a capacitor bottom electrode, a thin layer of titanium oxide can be deposited before forming the platinum, to provide a structure in which the titanium oxide is on the bottom portion of the trench. A high-dielectric-constant insulator is then formed over that structure by the Chemical Vapor Deposition. The high-dielectric-constant insulator has a composition which satisfies the stoichiometric composition over the platinum and which has more titanium atoms than those of the stoichiometric composition on the trench bottom. The resulting non-stoichiometric composition layer formed on the trench bottom has a low dielectric constant and a high insulation to maintain electric insulation between adjoining bottom capacitor electrodes. Because of a low crystallization, moreover, a layer having a planarized morpholo…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.