Random access memory device with trench-type one-transistor memory cell structure
US5736760A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 15, 1996 |
| Grant date | Apr 7, 1998 |
| Priority date | — |
| Expiry date | Apr 15, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/37
Abstract
A MOS random access memory device includes a semiconductor substrate having a trench formed therein, and an array of memory cells on the substrate. Each of the memory cells includes a 1-bit data-storage capacitor and a transfer-gate MOS transistor. The capacitor includes an insulated layer buried in the trench, which serves as a storage node. An island-shaped semiconductor layer covers the storage-node layer at least partially on the substrate, and is coupled thereto. The transistor has a source and a drain defining a channel region therebetween in the substrate, and an insulated gate overlying the channel region. One of the source and drain is directly coupled to the island-shaped layer, while the other of them is contacted with a corresponding data-transfer line (bit line) associated therewith.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.