DRAM cell arrangement and method for its manufacture

US5736761A · kind A · utility

Assignee

• Siemens Aktiengesellschaft · DE

Inventors

• Lothar Risch · Neubiberg, DE
• Franz Hofmann · Munich, DE
• Wolfgang Roesner · Austin, US
• Wolfgang Krautschneider · Ottobrunn, DE

Key dates

• Filing date: May 14, 1996
• Grant date: Apr 7, 1998
• Expiry date: May 14, 2016

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B12/34

Abstract

The DRAM cell arrangement has one vertical MOS transistor per memory cell, whose first source/drain region adjoins a trenched bitline (5), whose gate electrode (13) is connected with a trenched wordline and whose second source/drain region (3) adjoins a substrate main surface (1). A capacitor dielectric (16), which is in particular a ferroelectric or paraelectric layer, is arranged on at least the second source/drain region and a capacitor plate (17) is arranged on the dielectric, so that the second source/drain region (3) acts additionally as a memory node. The DRAM cell arrangement can be manufactured with a memory cell surface of 4 F.sup.2.