Cache tag system for use with multiple processors including the most recently requested processor identification
US5737757A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 23, 1997 |
| Grant date | Apr 7, 1998 |
| Priority date | — |
| Expiry date | Jan 23, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0822
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A shared memory multiprocessor computer system in which one or more processor modules and/or input/output modules have cache memories. The main memory controller for each main memory of the system maintains a duplicate cache tag array containing current information on the status of data lines from the main memory that are stored in the cache memories. Thus, coherency checks can be performed directly by the main memory controller. This eliminates the need for each processor having a cache memory to perform a separate coherency check and to communicate the results of its coherency checks to the main memory controller, and thereby reduces delays associated with processing coherent transactions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.