Method and apparatus for maintaining cache coherency in a computer system with a highly pipelined bus and multiple conflicting snoop requests
US5737758A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Apr 4, 1997 |
| Grant date | Apr 7, 1998 |
| Priority date | — |
| Expiry date | Apr 4, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0833
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An efficient method for handling multiple conflicting snoop requests with minimal stalling on the external bus by using blocking conditions to maintain and update a snoop queue for maintaining cache coherence in a computer system with caching units. An entry in a snoop queue is allocated to a snoopable request which has an associated snoop address. The snoop address is compared with addresses corresponding to previously allocated entries stored in the snoop queue. A block condition is set if there is a match between the snoop address and one or more of the addresses stored in the snoop queue. One or more history bits are set in the snoop queue indicating a chronological ordering of the entry in the snoop queue. A snoop operation corresponding to the snoop request is blocked until the block condition is cleared.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.