Apparatus and method for detecting defects in insulative layers of MOS active devices
US5739052A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 4, 1996 |
| Grant date | Apr 14, 1998 |
| Priority date | — |
| Expiry date | Sep 4, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L22/12
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A technique for quantifying the effect of plasma etching during the formation of MOS transistors avoids the problems of prior techniques. A modified MOS capacitor 40 comprising a dielectric 12 separating a conductive plate 18 having a conductive sidewall 24 from a conductive substrate 10 is formed using the same or similar steps as a MOS transistor. Dielectric layer 12, such as oxide, is formed over a portion of conductive substrate 10. Conductive capacitor plate 18 is formed over a portion of the dielectric layer 12 using a plasma etch to remove unwanted material. After forming capacitor plate 18, the area of capacitor plate 18 is modified to encompass a peripheral oxide region 20. The modification consists of placing a conductive sidewall 24 of the same material as capacitor plate 18 or of other conductive materials around the periphery of capacitor plate 18. Electrical characterization is performed on modified MOS capacitor 40 yielding information about damage to the oxide in peripheral region 24 caused by the plasma etch. Modified MOS capacitor 40 can be used to compare plasma chemistries, detect oxide trenching, detect etchant loading and determine the effect of process hardwa…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.