Dielectrically isolated substrate and method for manufacturing the same
US5739575A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 30, 1996 |
| Grant date | Apr 14, 1998 |
| Priority date | — |
| Expiry date | Aug 30, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/74
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Element isolation technique for LSIs having a fine pattern of sub-micron class or finer. A high strained region doped with impurities at a high concentration is formed under, and remote from, a buried insulating material (dielectrics) layer for element isolation. With this buried dielectrics element isolation (BDEI) structure, since the high strained layer exists just under the buried dielectrics layer, crystal defects generated near the buried dielectrics layer due to strain caused by a difference of thermal expansion coefficient between a semiconductor layer and the buried dielectrics layer, are moved toward the high strained layer. Accordingly, the crystal defects do not reach an active region where active elements are formed, so that leakage current in the p-n junction formed in the active layer can be advantageously reduced.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.