ESD protection system for an integrated circuit with multiple power supply networks
US5740000A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 30, 1996 |
| Grant date | Apr 14, 1998 |
| Priority date | — |
| Expiry date | Sep 30, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH02H9/046
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
An ESD protection system for protecting a CMOS integrated circuit (IC) with multiple power supplies is provided. The ESD protection system uses on-chip diodes to route ESD current from a first IC pin to the main positive power supply, where it is partly absorbed by the parasitic capacitance between the positive supply and ground. A charge sharing diode is provided between the main power supply and the clean power supply networks so that more of the ESD current may be absorbed by the parasitic capacitance between the clean power supply networks and ground. A core shunt circuit, which turns on when an ESD event is sensed, is provided to directly shunt ESD current from the positive supply to ground. Another diode is used to route current from the ground network out a second IC pin.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.