Printing and adhering patterned metal on laid-up multi-layer green wafer before firing so as to later form precise integral co-fired conductive traces and pads on top and bottom surfaces of monolithic, buried-substrate, capacitors
US5740010A · kind A · utility
Inventors
Key dates
| Filing date | Sep 15, 1995 |
| Grant date | Apr 14, 1998 |
| Priority date | — |
| Expiry date | Sep 15, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3025
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
Metal, normally gold or platinum, is printed, and is adhered by a glass frit, on the top and/or bottom surfaces of a multi-layer laid-up green ceramic wafers containing typically up to 16 layers and 800+ separate devices, typically 800+ monolithic, buried-substrate, ceramic multiple capacitors. The wafer is diced, and the multiple ceramic capacitors each with its patterned surface metal are co-fired. The integrally formed, top and bottom surface, conduction traces connect similarly formed pads, typically disposed in a "pin-grid" pattern, to later-added side traces or conductive castellations that connect to the electrodes of multiple buried-substrate capacitors. The pads are precisely located, and extend over such ample areas, to support the stable surface mounting, and the reliable electrical connection of, diverse external electrical circuits and components. The surface mounting may be by and of adhering with conductive adhesive, soldering, reflow soldering, gold wire bonded, aluminum wire bonding, flip-chip mounting, die bonding and like processes, including automated processes. The pads on the bottom surface typically support mounting the ceramic multiple capacitor to a printed…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.