Electrically programmable memory cell
US5740103A · kind A · utility
1Cited by
8References
6Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 6, 1997 |
| Grant date | Apr 14, 1998 |
| Priority date | — |
| Expiry date | Mar 6, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/5612
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An electrically programmable cell comprises a substrate of the first conductivity type having a channel region, a control gate on a first insulating layer above the channel region, a source region and a drain region of a second conductivity type, on both sides of the channel region, at least the drain region including a low-doped region adjacent to the channel, a floating gate on a second insulating layer above at least a portion of said low-doped region. The thickness of the second insulating layer is lower than the thickness of the first insulating layer and is low enough for having charge transfers through tunnel effect.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.