Redundant memory cell selecting circuit having fuses coupled to memory cell group address and memory cell block address
US5740114A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 10, 1995 |
| Grant date | Apr 14, 1998 |
| Priority date | — |
| Expiry date | May 10, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/844
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus for selecting redundant memory cells in integrated circuit memory devices. The apparatus includes eight memory cell blocks, each of which includes a plurality of memory cell groups, a redundant memory cell group of a first set and a redundant memory cell group of a second set; and eight selecting fuse circuit blocks. Four of the selecting fuse circuit blocks are coupled to the memory cell blocks and adapted to select a redundant word line group of the first set of any of the eight memory cell blocks, and the other four selecting fuse circuit blocks are coupled to the memory cell blocks and adapted to select a redundant word line group of the second set of any of the eight memory cell blocks.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.