Modified L1/L2 cache inclusion for aggressive prefetch
US5740399A · kind A · utility
45Cited by
15References
5Claims
0Family size
Assignee
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Key dates
| Filing date | Aug 23, 1995 |
| Grant date | Apr 14, 1998 |
| Priority date | — |
| Expiry date | Aug 23, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0897
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Within a data processing system implementing L1 and L2 caches and stream filters and buffers, prefetching of cache lines is performed in a progressive manner. In one mode, data may not be prefetched. In a second mode, two cache lines are prefetched wherein one line is prefetched into the L1 cache and the next line is prefetched into a stream buffer. In a third mode, more than two cache lines are prefetched at a time. In the third mode cache lines may be prefetched to the L1 cache and not the L2 cache, resulting in no inclusion between the L1 and L2 caches.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.