Method of generating power vectors for circuit power dissipation simulation having both combinational and sequential logic circuits
US5740407A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 5, 1995 |
| Grant date | Apr 14, 1998 |
| Priority date | — |
| Expiry date | Jul 5, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/33
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of generating power vectors to calculate power dissipation for a circuit is provided. The circuit includes both combinational logic and sequential logic circuits. The method includes removing all sequential logic circuits from the circuit. Boolean equations that describe the logical operation of the combinational logic of the circuit cells are generated. Power vectors are generated from the Boolean equations corresponding to internal and output transitions which dissipate power in the circuit. Redundant power vectors are then eliminated. The power vectors are then analyzed for "consistent" behavior with the sequential logic circuits. Operation of sequential logic circuits follow an ordered or defined sequence of events. Power vectors that are "inconsistent" with the operation of the sequential logic circuits are eliminated. The remaining power vectors are used to simulate the power dissipation of the circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.