Punchthrough-triggered ESD protection circuit through gate-coupling

US5742084A · kind A · utility

Assignee

• UNITED MICROELECTRONICS CORP. · TW

Inventor

• Ta-Lee Yu · Shanghai, CN

Key dates

• Filing date: Jul 23, 1996
• Grant date: Apr 21, 1998
• Expiry date: Jul 23, 2016

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L2924/0002

Abstract

A punchthrough-triggered ESD protection circuit which disposes an NMOS transistor at the anode gate of an lateral silicon-controlled rectifier, and a control circuit which provides a gate voltage for the gate of the NMOS transistor. By changing the channel length of the NMOS transistor as well as the gate voltage, the punchthrough voltage of the NMOS transistor is readily adjusted to a predetermined level. When ESD stress is present at the IC pad, the NMOS transistor goes into breakdown because of punchthrough and then triggers on the lateral silicon controlled rectifier. Thus, the trigger voltage of the ESD voltage can be lowered to the punchthrough voltage of the NMOS transistor. Accordingly, the ESD stress at the IC pad is bypassed by the conduction of the ESD protection circuit to allow an internal circuit to be protected from ESD damage.