Low-voltage trigger electrostatic discharge protection circuit

US5742085A · kind A · utility

Assignee

• UNITED MICROELECTRONICS CORP. · TW

Inventor

• Ta-Lee Yu · Shanghai, CN

Key dates

• Filing date: Nov 25, 1996
• Grant date: Apr 21, 1998
• Expiry date: Nov 25, 2016

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D89/713

Abstract

A low-voltage trigger electrostatic discharge protection circuit with different layout structure, smaller chip area for better performance and space saving is connected, to the bonding pad of an IC to protect an internal circuit of an IC from electrostatic discharge damage using at least one NMOS transistor and at least two SCR connected in parallel between the bonding pad and a circuit ground point. When the electrostatic discharge stress is applied to the bonding pad, the NMOS will breakdown before breakdown of the gate oxide layer of the internal circuit to trigger the SCRs into snapback mode operation. Then the electrostatic discharge stress on the bonding pad is released by two SCRs (or more). Because the electrostatic discharge stress can be released by two SCRs at the same time, the invention can protect the SCRs from damage as well rather than the prior art using just one SCR and lead to better ESD performance. Furthermore, the chip area of the invention is about 150 .mu.m.sup.2 smaller than that of prior art for space saving. For more precise statement, the invention provides about 10% chip area saving.