Non-volatile memory cells using only positive charge to store data
US5742542A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 3, 1995 |
| Grant date | Apr 21, 1998 |
| Priority date | — |
| Expiry date | Jul 3, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/0441
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An improved EEPROM structure is provided which has a longer data retention period. This is achieved by utilizing only positive charges to store data on the floating gate. The EEPROM structure includes a write select transistor (112), a read select transistor (120), and a floating gate sense transistor (126). The source of the write select transistor is capacitively coupled to the floating gate of the floating gate sense transistor via a tunnel oxide layer (145). The floating gate of the floating gate sense transistor is also capacitively coupled to a control gate line (CG) via a gate oxide layer (153). The sense transistor is formed as an enhancement transistor so as to allow the EEPROM structure to be operated in a region where the floating gate potential is positive for both programmed and erased conditions, thereby using only the positive charges to store data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.