Method and device for address decoding in an integrated circuit memory
US5742546A · kind A · utility
5Cited by
4References
20Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Sep 11, 1995 |
| Grant date | Apr 21, 1998 |
| Priority date | — |
| Expiry date | Sep 11, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/18
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a method for the decoding of the addresses of a memory, a pulse is generated at output of a filtering circuit at each change of address detected at the address bus to inhibit the address decoder during a determined duration. The filtering signal is applied more particularly to the row decoder which selects a row corresponding to an address applied to the input of the decoder and applies a control voltage to this row. This method is particularly advantageous in low-voltage memories.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.